1. Field of the Invention
The present invention generally relates to comparator circuits. More particularly, this invention relates to a circuit and a method for differential comparators with hysteresis.
2. Description of the Prior Art
FIG. 1 shows a prior art comparator circuit without hysteresis. It is a simple operational amplifier (op amp). The figure shows a differential comparator circuit. Devices 110 and 120 are p-channel metal oxide semiconductor field effect transistors (PMOS FETs). They are load devices with their sources and substrates connected to the power supply node 111. The gates of devices 110 and 120 are connected in common to the rain 114 of device 120. The drain 118 of device 110 drives inverter 180. The output of inverter 180 is node Out 0B (117). The output of inverter 180 feeds inverter 190, whose output is Out0 (116). N-channel metal oxide semiconductor field effect transistors (NMOSFETs) 130 and 140 are the logic devices for the differential amplifier. The gate of device 130 is connected to a reference voltage, VREF, 150. The drain of device 130 is connected to node 118. The gate of device 140 is connected to an input voltage, VIN 160. The drain of device 140 is connected to node 114. The sources of devices 130 and 140 are connected in common to the drain 113 of NMOS FET device 115. Device 115 is a current source whose current is specified by its device size and gate voltage, MNVT 170. The source of device 115 is connected to ground 112.
FIG. 1b shows a transfer function plot 122 with VIN vs. OUT0. Increasing VIN from zero, the output of the differential Op amp remains zero until VIN approaches VREF121. As VIN approaches VREF, Out0 begins to increase from zero. Out0 continues to increase until VIN is slightly above VREF. Then, Out0 stops increasing and remains constant at a HIGH level.
Similarly, in FIG. 1b as VIN decreases from some voltage level above VREF, Out0 remains at a constant HIGH level. As VIN decreases and approaches VREF, Out0 decreases. Out0 decreases to zero as VIN decreases to a voltage value just below VREF. Then, as VIN decreases toward zero, Out0 remains constant at zero volts as shown in FIG. 1b. As we see from this description, the comparator circuit of FIG. 1a does not have hysteresis.
A problem with comparator circuits, which do not have hysteresis, is that they are poor for measuring temperatures or other quantities, which have alternating fluctuation.
U.S. Pat. No. 6,459,306 B1 (Fischer et al.) describes a low power differential comparator with stable hysteresis. The input stage bias is used for both setting a bias level and for setting the hysteresis level of the differential comparator circuit. This multiple use of the input stage bias helps to reduce the overall current and power requirements while maintaining full operating speed.
U.S. Pat. No. 6,366,136 B1 (Page) discloses a voltage comparator with hysteresis that includes a differential amplifier, voltage divider circuits and a current mirror. The input terminals of the two differential amplifier circuit branches are biased at unequal potentials by the voltage divider circuits. The output of the current mirror circuit can be implemented to include multiple branches which are selectively connectable. This allows the user to selectively vary the amount of hysteresis as a function of the differences in the input signal voltage necessary to cause the conducting differential amplifier circuit branches to alternate.
U.S. Pat. No. 6,362,467 B1 (Bray) describes a fast-switching comparator with hysteresis. Fast switching is achieved in the comparator by driving the comparator stage with a gain amplifier and feeding back the output signal from the comparator to the gain amplifier.